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BDLC M68HC12B(pdf 490)英文.rar

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欧亿·体育(中国)有限公司大小:2077KB(压缩后)
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更新时间:2015/3/11(发布于上海)

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文本描述
Features include: • 16-bit CPU12: – Upwardly compatible with the M68HC11 instruction set – Interrupt stacking and programmer’s model identical to the M68HC11 – 20-bit arithmetic logic unit (ALU) – Instruction queue – Enhanced indexed addressing – Fuzzy logic instructions • Multiplexed bus: – Single chip or expanded – 16-bit by 16-bit wide or 16-bit by 8-bit narrow modes • Memory: – 32-Kbyte FLASH electrically erasable, programmable read-only memory (EEPROM) with 2-Kbyte erase-protected boot block — MC68HC912B32 and MC68HC912BC32 only – 32-Kbyte ROM — MC68HC12BE32 and MC68HC12BC32 only – 768-byte EEPROM – 1-Kbyte random-access memory (RAM) with single-cycle access for aligned or misaligned read/write • 8-channel, 10-bit analog-to-digital converter (ATD) • 8-channel standard timer module (TIM) — MC68HC912B32 and MC68HC(9)12BC32 only: – Each channel fully configurable as either input capture or output compare – Simple pulse-width modulator (PWM) mode – Modulus reset of timer counter 中国最大的欧亿·体育(中国)有限公司库下

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